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83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer product specification supersedes data of 1998 jan 06 ic20 data handbook 1998 jun 04 integrated circuits
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 2 1998 jun 04 853-2067 19495 features ? 80c51 based architecture 8k 8 rom (83c576) 8k 8 eprom (87C576) 256 8 ram 10-bit, 6 channel a/d three 16-bit counter/timers 2 pwm outputs programmable counter array universal peripheral interface enhanced uart oscillator fail detect low active reset 4 analog comparators watchdog timer low v cc detect power-on detect ? memory addressing capability 64k rom and 64k ram ? power control modes: idle mode power-down mode ? cmos and ttl compatible ? 6 to 16mhz ? extended temperature ranges ? otp available ? that can be programmed in circuit ? software reset ? 15 source, 2 level interrupt structure ? lower emi noise ? programmable i/o pins ? serial on-board programming ? schmitt trigger inputs on port 1 description the philips 83c576/87C576 is a high-performance microcontroller fabricated with philips high-density cmos technology. the philips cmos technology combines the high speed and density characteristics of hmos with the low power attributes of cmos. philips epitaxial substrate minimizes latch-up sensitivity. the 8xc576 contains an 8k 8 rom (83c576) eprom (87C576), a 256 8 ram, 32 i/o lines, three 16-bit counter/timers, a programmable counter array (pca), a 10-bit, 6 channel a/d, 2 pwm outputs, an 8-bit upi interface, a fifteen-source, two-priority level nested interrupt structure, an enhanced uart, four analog comparators, power-fail detect and oscillator fail detect circuits, and on-chip oscillator and clock circuits. in addition, the 8xc576 has a low active reset, and a software reset. there is also a fully configurable watchdog timer, and internal power on clear circuit. the part includes idle mode and power-down mode states for reduced power consumption. ordering information rom eprom 1 temperature range c and package freq (mhz) drawing number p83c576ebp n p87C576ebpn otp 0 to +70, 40-pin plastic dual in-line package 16 sot129-1 p83c576eba a p87C576ebaa otp 0 to +70, 44-pin plastic leaded chip carrier 16 sot187-2 p83c576ebb b p87C576ebbb otp 0 to +70, 44-pin plastic quad flat pack 16 sot307-2 p83c576efp n p87C576ebpn otp 40 to +85, 40-pin plastic dual in-line package 16 sot129-1 p83c576efa a p87C576efa a otp 40 to +85, 44-pin plastic leaded chip carrier 16 sot187-2 p83c576efb b p87C576efbb otp 40 to +85, 44-pin plastic quad flat pack 16 sot307-2 p83c576ehpn p87C576ehpn otp 40 to +125, 40-pin plastic dual in-line package 16 sot129-1 p83c576ehaa p87C576ehaa otp 40 to +125, 44-pin plastic leaded chip carrier 16 sot187-2 p83c576ehbb p87C576ehbb otp 40 to +125, 44-pin plastic quad flat pack 16 sot307-2 note: 1. otp - one time programmable eprom.
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 3 block diagram psen ea ale rst xtal1 xtal2 v cc v ss port 0 drivers port 2 drivers ram addr register ram port 0 latch port 2 latch rom/ eprom register b acc tmp2 tmp1 alu timing and control instruction register pd oscillator psw port 1 latch port 3 latch port 1 drivers port 3 drivers program address register buffer pc incre- menter program counter dptr p1.0-p1.5 p3.0-p3.7 p0.0-p0.7 p2.0-p2.7 stack pointer sfrs timers pca 10-bit analog to digital converter su00255b upi control low voltage detect power on detect ab watchdog timer a b clk and osc failure detect comparator block pwm av ss +av cc
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 4 logic symbol port 0 port 1 port 2 port 3 address and data bus address bus rxd txd int0 int1 t0 t1 wr rd secondary functions rst ea /v pp psen ale/prog v ss v cc xtal1 xtal2 cmp1+ cmpr cmp0+ cmp0 cmp3+ cmp2+ secondary functions db0 db1 db2 db3 db4 db5 db6 db7 adin0 adin1 adin2 adin3 adin4 adin5 pwm1/eci cex4/pwm0 t2/cs# t2ex/a0 cex3/cmp3 cex2/cmp2 cex1/cmp1 cex0/cmp0 su00254a pin configurations 44-pin plastic quad flat pack pin function 1 adin3/p1.3 2 adin4/p1.4 3 adin5/p1.5 4 rst 5 rxd/p3.0 6 nc* 7 txd/p3.1 8 int 0/p3.2/cmp3+ 9 int 1/p3.3/cmp2+ 10 t0/p3.4/cmp1+ 11 t1/p3.5/cmpr 12 wr /p3.6/cmp0+ 13 rd /p3.7cmp0 14 xtal2 15 xtal1 su00253b pin function 31 p0.6/ad6/db6 32 p0.5/ad5/db5 33 p0.4/ad4/db4 34 p0.3/ad3/db3 35 p0.2/ad2/db2 36 p0.1/ad1/db1 37 p0.0/ad0/db0 38 v cc 39 nc* 40 +v ref /av cc 41 v ref /av ss 42 adin0/p1.0 43 adin1/p1.1 44 adin2/p1.2 pqfp 44 34 1 11 33 23 12 22 pin function 16 v ss 17 nc* 18 p2.0/a8/cex0/cmp0 19 p2.1/a9/cex1/cmp1 20 p2.2/a10/cex2/cmp2 21 p2.3/a11/cex3/cmp3 22 p2.4/a12/t2ex/a0 23 p2.5/a13/t2/cs 24 p2.6/a14/cex4/pwm0 25 p2.7/a15/pwm1/eci 26 psen 27 ale/prog 28 nc* 29 ea /v pp 30 p0.7/ad7/db7 * no internal connection plastic leaded chip carrier lcc 6140 7 17 39 29 18 28 pin function 31 p2.7/a15/pwm1/eci 32 psen 33 ale/prog 34 nc* 35 ea /v pp 36 p0.7/ad7/db7 37 p0.6/ad6/db6 38 p0.5/ad5/db5 39 p0.4/ad4/db4 40 p0.3/ad3/db3 41 p0.2/ad2/db2 42 p0.1/ad1/db1 43 p0.0/ad0/db0 44 v cc su00252a pin function 16 t0/p3.4/cmp1+ 17 t1/p3.5/cmpr 18 wr /p3.6/cmp0+ 19 rd /p3.7/cmp0 20 xtal2 21 xtal1 22 v ss 23 nc* 24 p2.0/a8/cex0/cmp0 25 p2.1/a9/cex1/cmp1 26 p2.2/a10/cex2/cmp2 27 p2.3/a11/cex3/cmp3 28 p2.4/a12/t2ex/a0 29 p2.5/a13/t2/cs 30 p2.6/a14/cex4/pwm0 pin function 1 nc* 2+v ref /av cc 3v ref /av ss 4 adin0/p1.0 5 adin1/p1.1 6 adin2/p1.2 7 adin3/p1.3 8 adin4/p1.4 9 adin5/p1.5 10 rst 11 rxd/p3.0 12 nc* 13 txd/p3.1 14 int 0/p3.2/cmp3+ 15 int 1/p3.3/cmp2+ * no internal connection
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 5 pin descriptions pin number mnemonic dip lcc qfp type name and function v ss 20 22 16 i ground: 0v reference. v cc 40 44 38 i power supply: this is the power supply voltage for normal, idle, and power-down operation. p0.0-0.7 39-32 43-36 37-30 i/o port 0: port 0 is a bidirectional i/o port. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory (see note 5). in this application, it uses strong internal pull-ups when emitting 1s. port 0 also receives code bytes during parallel eprom programming and outputs code bytes during verification. external pull-ups are required during program verification. during reset, the port register is loaded with 1's. port 0 has 4 output modes selected on a per bit basis by writing to the p0m1 and p0m2 special function registers as follows: p0m1.x p0m2.x mode description 0 0 open drain (default). see note 1. 0 1 weak pullup. see note 2. 1 0 high impedance. see note 3. 1 1 push-pull. see note 4. port 0 is also the data i/o port for the universal peripheral interface (upi). when the upi is enabled, port 0 must be configured as high-z by the user. input/output through p0 is controlled by pin cs , wr , rd , and a0. output is push-pull when enabled. p1.0-p1.5 3-8 5-9 42-44 1-3 i/o port 1: port 1 is a 6-bit bidirectional i/o port with schmitt trigger inputs. port 1 receives the control signals during program memory verification and parallel eprom programming. during reset, port 1 is configured as a high impedance analog input port. digital push-pull outputs are enabled by writing 1's to the p1m1 register. the programmer must take care to prevent digital outputs from switching while an a/d conversion is in progress. port 1 has 3 output modes selected on a per bit basis by writing to the p1m1 and p1m2 special function registers as follows: p1m1.x p1m2.x mode description 0 0 a/d only. (high impedance) 0 1 digital input only. high impedance (default). 1 x push-pull. port 1 pins also serve alternate functions as follows: 3 4 42 i/o p1.0/adin0 4 5 43 i/o p1.1/adin1 5 6 44 i/o p1.2/adin2 6 7 1 i/o p1.3/adin3 7 8 2 i/o p1.4/adin4 8 9 3 i/o p1.5/adin5 p2.0-p2.7 21-28 24-31 18-25 i/o port 2: port 2 is an 8-bit bidirectional i/o port. port 2 emits the high-order address byte during accesses to external program and data memory that use 16-bit addresses (movx @dptr) (see note 5). in this application, it uses strong internal pull-ups when emitting 1s. port 2 receives the high-order address byte during program verification and parallel eprom programming. during reset, the port 2 pullups are turned on synchronously, and the port register is loaded with 1's. port 2 has the following output modes which can be selected on a per bit basis by writing to p2m1 and p2m0: p2m1.x p2m2.x mode description 0 0 open drain. see note 1. 0 1 weak pullup (default). see note 2. 1 0 high impedance. see note 3. 1 1 push-pull. see note 4. port 2 pins serve alternate functions as follows: 21 24 18 p2.0 cex0 pca module 0 external i/o cmp0 comparator 0 output 22 25 19 p2.1 cex1 pca module 1 external i/o cmp1 comparator 1 output 23 26 20 p2.2 cex2 pca module 2 external i/o cmp2 comparator 2 output 24 27 21 p2.3 cex3 pca module 3 external i/o cmp3 comparator 3 output 25 28 22 p2.4 t2ex timer 2 capture input a0 upi address input 26 29 23 p2.5 t2 timer 2 external i/o e clock-out (programmable) cs upi chip select input 27 30 24 p2.6 cex4 pca module 4 external i/o pwm0 pulse width modulator 0 output 28 31 25 p2.7 eci pca count input pwm1 pulse width modulator 1 output
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 6 pin descriptions (continued) pin number mnemonic dip lcc qfp type name and function +v ref /av cc 1 2 40 i a/d positive power supply v ref /av ss 2 3 41 i a/d 0v reference p3.0-p3.7 10-17 11, 13-19 5, 7-13 i/o port 3: port 3 is an 8-bit bidirectional i/o port. port 3 pins that have 1s written to them can be used as inputs but will source current when externally pulled low (see dc electrical characteristics: i il ). during reset all pins will be synchronously driven high and will remain high until written to by software. port 3 has the following output modes which can be selected on a per bit basis by writing to p3m1 and p3m2: p3m1.x p3m2.x mode description 0 0 open drain. see note 1. 0 1 weak pullup (default). see note 2. 1 0 high impedance. see note 3. 1 1 push-pull. see note 4. port 3 pins serve alternate functions as follows: 10 11 5 i p3.0 rxd serial receive port 11 13 7 o p3.1 txd serial transmit port (enabled only when transmitting serial data) 12 14 8 i p3.2 int0 external interrupt 0 cmp3+ comparator 3 positive input 13 15 9 i p3.3 int1 external interrupt 1 cmp2+ comparator 2 positive input 14 16 10 i p3.4 t0 timer/counter 0 input cmp1+ comparator 1 positive input 15 17 11 i p3.5 t1 timer/counter 1 input cmpr common reference to comparators 1, 2, 3 16 18 12 o p3.6 wr external data memory write strobe cmp0+ comparator 0 positive input 17 19 13 o p3.7 rd external data memory read strobe cmp0 comparator 0 negative input rst 9 10 4 i reset: a low on this pin synchronously resets all port pins to a high state. the pin must be held low with the oscillator running for 24 oscillator cycles to initialize the internal registers. an internal diffused resistor to v cc permits a power on reset using only an external capacitor to v ss . rst has a schmitt trigger input stage to provide additional noise immunity with a slow rising input voltage. ale/prog 30 33 27 i/o address latch enable/program pulse: output pulse for latching the low byte of the address during an access to external memory. in normal operation, ale is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory. ale is switched off if the bit 0 in the auxr register (8eh) is set. this pin is also the program pulse input (prog ) during parallel eprom programming. (see also internal reset on page 24.) psen 29 32 26 o program store enable: the read strobe to external program memory. when the device is executing code from the external program memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory. psen is not activated during fetches from internal program memory. ea /v pp 31 35 29 i external access enable/programming supply voltage: ea must be externally held low to enable the device to fetch code from external program memory locations 0000h to 1fffh. if ea is held high, the device executes from internal program memory unless the program counter contains an address greater than 1fffh. this pin also receives the 12.75v programming supply voltage (v pp ) during eprom programming. if this pin is at v pp voltage during reset the device enters the in-circuit programming mode. xtal1 19 21 15 i crystal 1: input to the inverting oscillator amplifier and input to the internal clock generator circuits. xtal2 18 20 14 o crystal 2: output from the inverting oscillator amplifier. notes: 1. when open drain mode is selected, ports 0 and 2 have weak pulldowns to guarantee positive leakage current (see dc electrical characteristic i ih ). 2. when weak pullup mode is selected, ports bits that have 1's written to them can be used as inputs but will source current whe n externally pulled low (see dc electrical characteristic i il ). 3. when high impedance mode is selected, all pullups and pulldowns are turned off. the only current sourced or sunk by the pin i s the parasitic leakage current (see dc electrical characteristic i l2 or i lc , as applicable. 4. when push-pull mode is selected, strong pullups are on continuously when emitting 1's (see dc electrical characteristic v oh ). 5. when open-drain, weak pull-up, or push-pull mode is selected.
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 7 table 1. 87C576 special function registers symbol description direct address bit address, symbol, or alternative port function msb lsb reset value acc* accumulator e0h e7 e6 e5 e4 e3 e2 e1 e0 00h adc0h# a/d channel 0 msb aah 00h adc1h# a/d channel 1 msb abh 00h adc2h# a/d channel 2 msb ach 00h adc3h# a/d channel 3 msb adh 00h adc4h# a/d channel 4 msb aeh 00h adc5h# a/d channel 5 msb afh 00h adc0l# a/d channel 0 2-lsbits 9ah 00h adc1l# a/d channel 1 2-lsbits 9bh 00h adc2l# a/d channel 2 2-lsbits 9ch 00h adc3l# a/d channel 3 2-lsbits 9dh 00h adc4l# a/d channel 4 2-lsbits 9eh 00h adc5l# a/d channel 5 2-lsbits 9fh 00h adcon# a/d control b1h adf adce ad8m amod1 amod0 asca2 asca1 asca0 00h adcs# a/d channel select b2h 00h auxr# auxiliary 8eh srst txi lo ao xxxx0000b b* b register f0h f7 f6 f5 f4 f3 f2 f1 f0 00h ccap0h# module 0 capture high fah xxxxxxxxb ccap1h# module 1 capture high fbh xxxxxxxxb ccap2h# module 2 capture high fch xxxxxxxxb ccap3h# module 3 capture high fdh xxxxxxxxb ccap4h# module 4 capture high feh xxxxxxxxb ccap0l# module 0 capture low eah xxxxxxxxb ccap1l# module 1 capture low ebh xxxxxxxxb ccap2l# module 2 capture low ech xxxxxxxxb ccap3l# module 3 capture low edh xxxxxxxxb ccap4l# module 4 capture low eeh xxxxxxxxb ccapm0# module 0 mode dah ecom capp capn mat tog pwm eccf x0000000b ccapm1# module 1 mode dbh ecom capp capn mat tog pwm eccf x0000000b ccapm2# module 2 mode dch ecom capp capn mat tog pwm eccf x0000000b ccapm3# module 3 mode ddh ecom capp capn mat tog pwm eccf x0000000b ccapm4# module 4 mode deh ecom capp capn mat tog pwm eccf x0000000b df de dd dc db da d9 d8 ccon*# pca counter control d8h cf cr ccf4 ccf3 ccf2 ccf1 ccf0 00x00000b ch# pca counter high f9h 00h cl# pca counter low e9h 00h cmod# pca counter mode d9h cidl wdte cps1 cps0 ecf 00xxx000b c7 c6 c5 c4 c3 c2 c1 c0 cmp*# comparator c0h ec3dp ec2dp ec1dp ec0dp c3ro c2ro c1ro c0ro 00h cmpe# comparator enable 92h ec3tdc ec2tdc ec1tdc ec0tdc ec3o ec2o ec1o ec0o 00h dptr: data pointer (2 bytes) dph data pointer high 83h 00h dpl data pointer low 82h 00h af ae ad ac ab aa a9 a8 ie0*# interrupt enable 0 a8h ea ec et2 es et1 ex1 et0 ex0 00h ie1*# interrupt enable 1 e8h eob eib ead ec4 ec3 ec2 ec1 ec0 00h * sfrs are bit addressable. # sfrs are modified from or added to the 80c51 sfrs.
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 8 table 1. 87C576 special function registers (continued) symbol description direct address bit address, symbol, or alternative port function msb lsb reset value bf be bd bc bb ba b9 b8 ip0* interrupt priority 0 b8h ppc pt2 ps pt1 px1 pt0 px0 x0000000b ip1*# interrupt priority 1 f8h pob pib pad pc4 pc3 pc2 pc1 pc0 00h 87 86 85 84 83 82 81 80 p0* port 0 80h ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ffh 97 96 95 94 93 92 91 90 p1* port 1 90h adin5 adin4 adin3 adin2 adin1 adin0 ffh a7 a6 a5 a4 a3 a2 a1 a0 p2* port 2 a0h eci cex4 t2 t2ex cex3 cex2 cex1 cex0 ffh b7 b6 b5 b4 b3 b2 b1 b0 p3* port 3 b0h rd wr t1 t0 int1 int0 txd rxd ffh p0m1# port 0 output mode 1 84h 00h p0m2# port 0 output mode 2 85h 00h p1m1# port 1 output mode 1 94h 00h p1m2# port 1 output mode 2 95h 3fh p2m1# port 2 output mode 1 a4h 00h p2m2# port 2 output mode 2 a5h ffh p3m1# port 3 output mode 1 b4h 00h p3m2# port 3 output mode 2 b5h ffh pcon power control 87h smod1 smod0 osf 1 pof 1 lvf 1 wdt0f 1 pd idl 00xxxx00b d7 d6 d5 d4 d3 d2 d1 d0 psw* program status word d0h cy ac f0 rs1 rs0 ov p 00h pwcon# pwm control bch pwmf en/clr pwe1 pwe0 00h pwmp# pwm prescaler bdh 00h pwm0# pwm register 0 beh 00h pwm1# pwm register 1 bfh 00h racap2h# timer 2 capture high cbh 00h racap2l# timer 2 capture low cah 00h saddr# slave address a9h 00h saden# slave address mask b9h 00h sbuf serial data buffer 99h xxxxxxxxb 9f 9e 9d 9c 9b 9a 99 98 scon* serial control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00h sp stack pointer 81h 07h 8f 8e 8d 8c 8b 8a 89 88 tcon* timer control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h cf ce cd cc cb ca c9 c8 t2con* timer 2 control c8h tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 00h t2mod# timer 2 mode control c9h t2oe 2 dcen xxxxxxx0b * sfrs are bit addressable. # sfrs are modified from or added to the 80c51 sfrs. 1. reset value depends on reset source. 2. programmable clock-out
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 9 table 1. 87C576 special function registers (continued) symbol description direct address bit address, symbol, or alternative port function msb lsb reset value th0 timer high 0 8ch 00h th1 timer high 1 8dh 00h th2# timer high 2 cdh 00h tl0 timer low 0 8ah 00h tl1 timer low 1 8bh 00h tl2# timer low 2 cch 00h tmod timer mode 89h gate c/t m1 m0 gate c/t m1 m0 00h ucs# upi control/status 86h st7 st6 st5 st4 ue af ibf obe/obf 00h wdcon # watchdog timer control c4h pre2 pre1 pre0 lvre ofre dpd wdrun wdmod 11111111b wdl# watchdog timer reload c1h 00h wfeed1# watchdog feed 1 c2h xxh wfeed2# watchdog feed 2 c3h xxh * sfrs are bit addressable. # sfrs are modified from or added to the 80c51 sfrs. 1. reset value depends on reset source. the 8xc576 has a number of failure detect circuits to prevent abnormal operating conditions. these failure detect circuits generate resets as shown in figure 1. power on clear / power on flag an on-chip power on detect circuit resets the 8xc576 and sets the power off flag (pcon.4) on power up or if v cc drops to zero momentarily. the pof can only be cleared by software. the rst pin is not driven by the power on detect circuit. the pof can be read by software to determine that a power failure has occurred and can also be set by software. low voltage detect an on-chip low voltage detect circuit sets the low voltage flag (pcon.3) if v cc drops below v low (see dc electrical characteristics) and resets the 8xc576 if the low voltage reset enable bit (wdcon.4) is set. if the lvre is cleared, the reset is disabled but lvf will still be set if v cc is low. the rst pin is not driven by the low voltage detect circuit. the lvf can be read by software to determine that v cc was low. the lvf can be set or cleared by software. oscillator fail detect an on-chip oscillator fail detect circuit sets the oscillator fail flag (pcon.5) if the oscillator frequency drops below oscf for one or more cycles (see ac electrical characteristics: oscf) and resets the 8xc576 if the oscillator fail reset enable bit (wdcon.3) is set. if ofre is cleared, the reset is disabled but osf will still be set if the oscillator fails. the rst pin is not driven by the oscillator fail detect circuit. the osf can be read by software to determine that an oscillator failure has occurred. the osf can be set or cleared by software. low active reset one of the most notable features on this part is the low active reset. the low active reset operates exactly the same as high active reset with the exception that the part is put into the reset mode by applying a low level to the reset pin. for power-on reset it is also necessary to invert the power-on reset circuit; connecting the 8.2k resistor from the reset pin to v cc and the 10 m f capacitor from the reset pin to ground. figure 1 shows the reset related circuitry. when reset the port pins on the 8xc576 are driven high synchronously. the 8xc576 also has low voltage detection circuitry that will, if enabled, force the part to reset when v cc (on the part) fails below a set level. low voltage reset is enabled by a normal reset. low voltage reset can be disabled by clearing lvre (bit 4 in the wdcon sfr) then executing a watchdog feed sequence (a5h to wfeed1 followed immediately by 5ah to wfeed2). in addition there is a flag (lvf) that is set if a low voltage condition is detected. the lvf flag is set even if the low voltage detection circuitry is disabled. notice that the low voltage detection circuitry does not drive the rst# pin so the lvf flag is the only way that the microcontroller can determine if it has been reset due to a low voltage condition. the 8xc576 has an on-chip power-on detection circuit that sets the pof (pcon.4) flag on power up or if the v cc level momentarily drops to 0v. this flag can be used to determine if the part is being started from a power-on (cold start) or if a reset has occurred due to another condition (warm start). the 8xc576 can be reset in software by setting the rst bit of the auxr register (auxr.3). see figure 1 for reset diagram.
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 10 pre2 pre1 pre0 lvre ofre dpd wdrun wdmod wdcon (c4h) shadow register for wdcon watchdog feed smod1 smod0 osf lvf wdtof pd idl pcon (87h) osc freq below oscf (min frequency) rst + v cc vlow (low v cc reference) power-on detect pca watchdog watchdog timer 8xc576 internal reset pof su00515b cidl wdte cps1 cps0 ecf cmod (d9h) srst txi lo ao auxr (8eh) shadow register wdte figure 1. reset circuitry timers the 8xc576 has four on-chip timers. timers 0 and 1 are identical in every way to timers 0 and 1 on the 80c51. timer 2 on the 8xc576 is identical to the 80c52 timer 2 (described in detail in the 80c52 overview) with the exception that it is an up or down counter. to configure the timer to count down the dcen bit in the t2mod special function register must be set and a low level must be present on the t2ex pin (p1.1). the pulse width modulator (pwm) system can be used as a timer by disabling its outputs and monitoring its counter overflow flag, the pwmf bit in the pwcon register (see the pwm section for details). the watchdog timer operation and implementation is similar to the 8xc550 (for additional information see the 8xc550 datasheet) with the exception that the reset values of the wdcon and wdl special function registers have been changed. the changes in these registers cause the watchdog timer to be enabled with a timeout of 16384 t osc when the part is reset. the watchdog can be disabled by executing a valid feed sequence and then clearing wdrun (bit 2 in the wdcon sfr). in timer mode, the timer is controlled by toggling the wdrun bit. the timeout flag, wdtof, is set when the timer overflows and must be cleared in software. programmable counter array (pca) the programmable counter array is a special timer that has five 16-bit capture/compare modules associated with it. each of the modules can be programmed to operate in one of four modes: rising and/or falling edge capture, software timer, high-speed output, or pulse width modulator. each module has a pin associated with it in port 2. module 0 is connected to p2.0(cex0), module 1 to p2.1(cex1), etc. the basic pca configuration is shown in figure 2. the pca timer is a common time base for all five modules and can be programmed to run at: 1/12 the oscillator frequency, 1/4 the oscillator frequency, the timer 0 overflow, or the input on the eci pin (p2.7). the timer count source is determined from the cps1 and cps0 bits in the cmod sfr as follows (see figure 3): cps1 cps0 pca timer count source 0 0 1/12 oscillator frequency 0 1 1/4 oscillator frequency 1 0 timer 0 overflow 1 1 external input at eci pin (p2.7) in the cmod sfr are three additional bits associated with the pca. they are cidl which allows the pca to stop during idle mode, wdte which enables or disables the watchdog function on module 4, and ecf which when set causes an interrupt and the pca overflow flag cf (in the ccon sfr) to be set when the pca timer overflows. these functions are shown in figure 3. the watchdog timer function is implemented in module 4 as implemented in other parts that have a pca that are available on the market. however, if a watchdog timer is required in the target application, it is recommended to use the hardware watchdog timer that is implemented on the 87C576 separately from the pca (see figure 15). the ccon sfr contains the run control bit for the pca and the flags for the pca timer (cf) and each module (refer to figure 6). to run the pca the cr bit (ccon.6) must be set by software. the pca is shut off by clearing this bit. the cf bit (ccon.7) is set when the pca counter overflows and an interrupt will be generated if the ecf bit in the cmod register is set, the cf bit can only be cleared by software. bits 0 through 4 of the ccon register are the flags for the m odules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. these flags
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 11 also can only be cleared by software. the pca interrupt system shown in figure 4. each module in the pca has a special function register associated with it. these registers are: ccapm0 for module 0, ccapm1 for module 1, etc. (see figure 7). the registers contain the bits that control the mode that each module will operate in. the eccf bit (ccapmn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the ccf flag in the ccon sfr to generate an interrupt when a match or compare occurs in the associated module. pwm (ccapmn.1) enables the pulse width modulation mode. the tog bit (ccapmn.2) when set causes the cex output associated with the module to toggle when there is a match between the pca counter and the module's capture/compare register. the match bit mat (ccapmn.3) when set will cause the ccfn bit in the ccon register to be set when there is a match between the pca counter and the module's capture/compare register. the next two bits capn (ccapmn.4) and capp (ccapmn.5) determine the edge that a capture input will be active on. the capn bit enables the negative edge, and the capp bit enables the positive edge. if both bits are set both edges will be enabled and a capture will occur for either transition. the last bit in the register ecom (ccapmn.6) when set enables the comparator function. figure 8 shows the ccapmn settings for the various pca functions. there are two additional registers associated with each of the pca modules. they are ccapnh and ccapnl and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. when a module is used in the pwm mode these registers are used to control the duty cycle of the output. pca capture mode to use one of the pca modules in the capture mode either one or both of the ccapm bits capn and capp for that module must be set. the external cex input for the module (on port 2) is sampled for a transition. when a valid transition occurs the pca hardware loads the value of the pca counter registers (ch and cl) into the module's capture registers (ccapnl and ccapnh). if the ccfn bit for the module in the ccon sfr and the eccfn bit in the ccapmn sfr are set then an interrupt will be generated. refer to figure 9. 16-bit software timer mode the pca modules can be used as software timers by setting both the ecom and mat bits in the modules ccapmn register. the pca timer will be compared to the module's capture registers and when a match occurs an interrupt will occur if the ccfn (ccon sfr) and the eccfn (ccapmn sfr) bits for the module are both set (see figure 10). high speed output mode in this mode the cex output (on port 2) associated with the pca module will toggle each time a match occurs between the pca counter and the module's capture registers. to activate this mode the tog, mat, and ecom bits in the module's ccapmn sfr must be set (see figure 11). pulse width modulator mode all of the pca modules can be used as pwm outputs. figure 12 shows the pwm function. the frequency of the output depends on the source for the pca timer. all of the modules will have the same frequency of output because they all share the pca timer. the duty cycle of each module is independently variable using the module's capture register ccapln. when the value of the pca cl sfr is less than the value in the module's ccapln sfr the output will be low, when it is equal to or greater than the output will be high. when cl overflows from ff to 00, ccapln is reloaded with the value in ccaphn. the allows updating the pwm without glitches. the pwm and ecom bits in the module's ccapmn register must be set to enable the pwm mode. pca interrupt system the pca on most 80c51 family devices provides a single interrupt source, ec (ie.6). the 8xc576 expands the flexibility of the pca by providing additional interrupt sources for each of the five pca modules, ec0 (ie1.0) through ec4 (ie1.4), in addition to the original interrupt source ec (ie.6). any of these sources can be enabled at any time. it is possible for both a module source (ec0 through ec4) to be enabled at the same time that the single source, ec, is enabled. in this case, a module event will generate an interrupt for both the module source and the single source, ec. module functions: 16-bit capture 16-bit timer 16-bit high speed output 8-bit pwm watchdog timer (module 4 only) module 0 module 1 module 2 module 3 module 4 p2.0/cex0 p2.1/cex1 p2.2/cex2 p2.3/cex3 p2.6/cex4 16 bits pca timer/counter time base for pca modules 16 bits su00578 figure 2. programmable counter array (pca)
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 12 cf cr ccf4 ccf3 ccf2 ccf1 ccf0 ccon (d8h) ch cl overflow interrupt 16bit up counter idle to pca modules cmod (d9h) cidl wdte cps1 cps0 ecf osc/12 osc/4 timer 0 overflow external input (p2.7/eci) decode 00 01 10 11 su00516 figure 3. pca timer/counter ie0.7 ea module 0 module 1 module 2 module 3 module 4 pca timer/counter cf cr ccf4 ccf3 ccf2 ccf1 ccf0 cmod.0 ecf to interrupt priority decoder ccon (d8h) ie1.0 ec0 su00579 ie0.7 ea ie1.1 ec1 ie0.7 ea ie0.6 ec ie0.7 ea ie1.2 ec2 ie0.7 ea ie1.3 ec3 ie0.7 ea ie1.4 ec4 ccapmn.0 eccfn to interrupt priority decoder to interrupt priority decoder to interrupt priority decoder to interrupt priority decoder to interrupt priority decoder figure 4. pca interrupt system
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 13 cmod address = od9h reset value = 00xx x000b cidl wdte cps1 cps0 ecf bit: symbol function cidl counter idle control: cidl = 0 programs the pca counter to continue functioning during idle mode. cidl = 1 programs it to be gated off during idle. wdte watchdog timer enable: wdte = 0 disables watchdog timer function on pca module 4. wdte = 1 enables it. not implemented, reserved for future use.* cps1 pca count pulse select bit 1. cps0 pca count pulse select bit 0. cps1 cps0 selected pca input** 0 0 0 internal clock, f osc 12 0 1 1 internal clock, f osc 4 1 0 2 timer 0 overflow 1 1 3 external clock at eci/p2.7 pin (max. rate = f osc 8) ecf pca enable counter overflow interrupt: ecf = 1 enables cf bit in ccon to generate an interrupt. ecf = 0 disables that function of cf. note: * user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new featur es. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. ** f osc = oscillator frequency su00686a 76543210 figure 5. cmod: pca counter mode register ccon address = od8h reset value = 00x0 0000b cf cr ccf4 ccf3 ccf2 ccf1 ccf0 bit addressable bit: symbol function cf pca counter overflow flag. set by hardware when the counter rolls over. cf flags an interrupt if bit ecf in cmod is set. cf may be set by either hardware or software but can only be cleared by software. cr pca counter run control bit. set by software to turn the pca counter on. must be cleared by software to turn the pca counter off. not implemented, reserved for future use*. ccf4 pca module 4 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf3 pca module 3 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf2 pca module 2 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf1 pca module 1 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. ccf0 pca module 0 interrupt flag. set by hardware when a match or capture occurs. must be cleared by software. note: * user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new featur es. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. su00036 76543210 figure 6. ccon: pca counter control register
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 14 ccapmn address ccapm0 0dah ccapm1 0dbh ccapm2 0dch ccapm3 0ddh ccapm4 0deh reset value = x000 0000b ecomn cappn capnn matn togn pwmn eccfn not bit addressable bit: symbol function not implemented, reserved for future use*. ecomn enable comparator. ecomn = 1 enables the comparator function. cappn capture positive, cappn = 1 enables positive edge capture. capnn capture negative, capnn = 1 enables negative edge capture. matn match. when matn = 1, a match of the pca counter with this module's compare/capture register causes the ccfn bit in ccon to be set, flagging an interrupt. togn toggle. when togn = 1, a match of the pca counter with this module's compare/capture register causes the cexn pin to toggle. pwmn pulse width modulation mode. pwmn = 1 enables the cexn pin to be used as a pulse width modulated output. eccfn enable ccf interrupt. enables compare/capture flag ccfn in the ccon register to generate an interrupt. note: *user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new featur es. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reserved bit is indeterminate. su00037 76543210 figure 7. ccapmn: pca modules compare/capture registers ecomn cappn capnn matn togn pwmn eccfn module function x 0 0 0 0 0 0 0 no operation x x 1 0 0 0 0 x 16-bit capture by a positive-edge trigger on cexn x x 0 1 0 0 0 x 16-bit capture by a negative trigger on cexn x x 1 1 0 0 0 x 16-bit capture by a transition on cexn x 1 0 0 1 0 0 x 16-bit software timer x 1 0 0 1 1 0 x 16-bit high speed output x 1 0 0 0 0 1 0 8-bit pwm x 1 0 0 1 x 0 x watchdog timer figure 8. pca module modes (ccapmn register)
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 15 cf cr ccf4 ccf3 ccf2 ccf1 ccf0 ccon (d8h) ecomn cappn capnn matn togn pwmn eccfn ccapmn, n= 0 to 4 (dah deh) ch cl ccapnh ccapnl cexn capture pca interrupt pca timer/counter 0 000 (to ccfn) su00749 figure 9. pca capture mode match cf cr ccf4 ccf3 ccf2 ccf1 ccf0 ccon (d8h) ecomn cappn capnn matn togn pwmn eccfn ccapmn, n= 0 to 4 (dah deh) ch cl ccapnh ccapnl pca interrupt pca timer/counter 00 00 16bit comparator (to ccfn) enable write to ccapnh reset write to ccapnl 01 su00750 figure 10. pca compare mode
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 16 cf cr ccf4 ccf3 ccf2 ccf1 ccf0 ccon (d8h) ecomn cappn capnn matn togn pwmn eccfn ccapmn, n: 0..4 (dah deh) ch cl ccapnh ccapnl pca interrupt pca timer/counter 10 00 16bit comparator (to ccfn) write to ccapnh reset write to ccapnl 01 enable cexn toggle match su00751 figure 11. pca high speed output mode cl < ccapnl ecomn cappn capnn matn togn pwmn eccfn ccapmn, n: 0..4 (dah deh) pca timer/counter 00 00 cl ccapnl cexn 8bit comparator overflow ccapnh enable 0 1 cl >= ccapnl 0 su00752 figure 12. pca pwm mode
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 17 watchdog timer the watchdog timer is not directly loadable by the user. instead, the value to be loaded into the main timer is held in an autoload register or is part of the mask rom programming. in order to cause the main timer to be loaded with the appropriate value, a special sequence of software action must take place. this operation is referred to as feeding the watchdog timer. to feed the watchdog, two instructions must be sequentially executed successfully. no intervening instruction fetches are allowed, so interrupts should be disabled before feeding the watchdog. the instructions should move a5h to the wfeed1 register and then 5ah to the wfeed2 register. if wfeed1 is correctly loaded and wfeed2 is not correctly loaded, then an immediate underflow will occur. the watchdog timer subsystem has two modes of operation. its principal function is a watchdog timer. in this mode it protects the system from incorrect code execution by causing a system reset when the watchdog timer underflows as a result of a failure of software to feed the timer prior to the timer reaching its terminal count. if the user does not employ the watchdog function, the watchdog subsystem can be used as a timer. in this mode, reaching the terminal count sets a flag. in most other respects, the timer mode possesses the characteristics of the watchdog mode. this is done to protect the integrity of the watchdog function. the watchdog timer subsystem consists of a prescaler and a main counter. the prescaler has 8 selectable taps off the final stages and the output of a selected tap provides the clock to the main counter. the main counter is the section that is loaded as a result of the software feeding the watchdog and it is the section that causes the system reset (watchdog mode) or time-out flag to be set (timer mode) if allowed to reach its terminal count. programming the watchdog timer both the eprom and rom devices have a set of sfrs for holding the watchdog autoload values and the control bits. the watchdog time-out flag is present in the pcon register and operates the same in all versions. in the eprom device, the watchdog parameters (autoload value and control) are always taken from the sfrs. in the rom device, the watchdog parameters can be mask programmed or taken from the sfrs. the selection to take the watchdog parameters from the sfrs or from the mask programmed values is controlled by ea (external access). when ea is high (internal rom access), the watchdog parameters are taken from the mask programmed values. if the watchdog is mask programmed to the timer mode, then the autoload values and the pre-scaler taps are taken from the sfrs. when ea is low (external access), the watchdog parameters are taken from the sfrs. the user should be able to leave code in his program which initializes the watchdog sfrs even though he has migrated to the mask rom part. this allows no code changes from eprom prototyping to rom coded production parts. the run control bit only functions in timer mode and does not require a feed sequence to modify. watchdog detailed operation eprom device (and romless operation: ea = 0) in the romless operation (rom part, ea = 0) and in the eprom device, the watchdog operates in the following manner (see figure 15). whether the watchdog is in the watchdog or timer mode, when external reset is applied, the following takes place: ? watchdog mode bit set to watchdog mode. ? watchdog is running. ? autoload register set to 00 (min. count). ? watchdog time-out flag is unchanged. ? prescaler is cleared. ? prescaler tap set to the highest divide. ? autoload takes place. the watchdog can be fed even though it is in the timer mode. note that the operational concept is for the watchdog mode of operation, when coming out of a hardware reset, the software should load the autoload registers, set the mode to watchdog, clear the watchdog timeout flag, and then feed the watchdog (cause an autoload). the watchdog will now be starting at a known point. if the watchdog is in the watchdog mode and running and happens to underflow at the time the external reset is applied, the watchdog time-out flag will be set. when the watchdog is in the watchdog mode and the watchdog underflows, the following action takes place (see figure 17): ? autoload takes place. ? watchdog time-out flag is set ? mode bit unchanged. ? watchdog run bit unchanged. ? autoload register unchanged. ? prescaler tap unchanged. ? all other device action same as external reset. note that if the watchdog underflows, the program counter will start from 00h as in the case of an external reset. the watchdog time-out flag can be examined to determine if the watchdog has caused the reset condition. the watchdog time-out flag bit must be cleared by software. when the watchdog is in the timer mode and the timer software underflows, the following action takes place: ? autoload takes place. ? watchdog time-out flag is set ? mode bit unchanged. ? watchdog run bit unchanged. ? autoload register unchanged. ? prescaler tap unchanged. mask rom device (ea = 1) in the mask rom device, the watchdog mode bit (wdmod) is mask programmed and the bit in the watchdog command register is read only and reflects the mask programmed selection. if the mask programmed mode bit selects the timer mode, then the watchdog run bit (wdrun) operates as described under eprom device. if the mask programmed bit selects the watchdog mode, then the watchdog run bit has no effect on the timer operation (see figure 16). watchdog function the watchdog consists of a programmable prescaler and the main timer. the prescaler derives its clock from the on-chip oscillator. the prescaler consists of a divide by 2 followed by a 13 stage upcounter with taps from stage 6 through stage 13. this is shown in figure 18.
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 18 the tap selection is programmable. the watchdog main counter is a down counter clocked (decremented) each time the programmable prescaler overflows. the watchdog generates an underflow signal (and is autoloaded) when the watchdog is at count 0 and the prescaler clock decrements the watchdog. the watchdog is 8 bits long and the autoload value can range from 0 to ffh. (the autoload value of 0 is permissible since the prescaler is cleared upon autoload). this leads to the following user design equations. definitions :t osc is the oscillator period, n is the selected prescaler tap value, w is the main counter autoload value, t min is the minimum watchdog time-out value (when the autoload value is 0), t max is the maximum time-out value (when the autoload value is ffh), t d is the design time-out value. t min = t osc 2 64 t max = t min 128 256 t d = t min 2 prescaler (w + 1) (where prescaler = 0, 1, 2, 3, 4, 5, 6, or 7) note that the design procedure is anticipated to be as follows. a t max will be chosen either from equipment or operation considerations and will most likely be the next convenient value higher than t d . (if the watchdog were inadvertently to start from 00h, an underflow would be guaranteed, barring other anomalies, to occur within t max ). the software must be written so that a feed operation takes place every t d seconds from the last feed operation. some tradeoffs may need to be made. it is not advisable to include feed operations in minor loops or in subroutines unless the feed operation is a specific subroutine. watchdog control register (wdcon) address c4h the following bits of this register are read only in the rom part when ea is high: wdmod, dpd, ofre, lvre, pre0, pre1, and pre2. that is, the register will reflect the mask programmed values. in the rom part with ea high, these bits are taken from mask coded bits and are not readable by the program. wdrun is read only in the rom part when ea is high and wdmod is in the watchdog mode. when wdmod is in the timer mode, wdrun functions normally. the parameters written into wdmod, dpd, ofre, lvre, pre0, pre1, and pre2 by the program are not applied directly to the watchdog timer subsystem. the watchdog timer subsystem is directly controlled by a second register which stores these bits. the transfer of these bits from the user register to the second control register takes place when the watchdog is fed. this prevents random code execution from directly foiling the watchdog function. this does not affect the operation where these bits are taken from mask coded values. the reset values of the wdcon and wdl registers will be such that the timer resets to the watchdog mode with a timeout period of 2 64 128 t osc . the watchdog timer does not generate an interrupt. additional bits in wdcon are used to disable reset generation by the oscillator fail and low voltage detect circuits. wdcon can be written by software only by executing a valid watchdog feed sequence. wdcon register bit definitions wdcon.7 pre2 prescaler select 2, reset to 1 wdcon.6 pre1 prescaler select 1, reset to 1 wdcon.5 pre0 prescaler select 0, reset to 1 wdcon.4 lvre low voltage reset enable, reset to 1 (enabled) wdcon.3 ofre oscillator fail reset enable, reset to 1 (enabled) wdcon.2 dpd disable power down wdcon.1 wdrun watchdog run, reset to 1 (enabled) wdcon.0 wdmod watchdog mode, reset to 1 (watchdog mode) enhanced uart the uart operates in all of the usual modes that are described in the first section of this book for the 80c51. in addition the uart can perform framing error detect by looking for missing stop bits, and automatic address recognition. the 8xc576 uart also fully supports multiprocessor communication as does the standard 80c51 uart. when used for framing error detect the uart looks for missing stop bits in the communication. a missing bit will set the fe bit in the scon register. the fe bit shares the scon.7 bit with sm0 and the function of scon.7 is determined by pcon.6 (smod0) (see figure 20). if smod0 is set then scon.7 functions as fe. scon.7 functions as sm0 when smod0 is cleared. when used as fe scon.7 can only be cleared by software. refer to figure 19. the serial port transmitter data can be inverted by setting the txi (auxr.2) bit. for normal operation, the txi bit should be cleared. automatic address recognition automatic address recognition is a feature which allows the uart to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. this feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. this feature is enabled by setting the sm2 bit in scon. in the 9 bit uart modes, mode 2 and mode 3, the receive interrupt flag (ri) will be automatically set when the received byte contains either the agiveno address or the abroadcasto address. the 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. automatic address recognition is shown in figure 21. the 8 bit mode is called mode 1. in this mode the ri flag will be set if sm2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a given or broadcast address. mode 0 is the shift register mode and sm2 is ignored.
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 19 su00711 txi txd int. bus write to latch dq p3.1 latch p3.1 pin programmable output buffer figure 13. txi (auxr.2) bit inverts the txd pin (p3.1) when set ecomn cappn capnn matn togn pwmn eccfn ccapm4 (deh) ch cl ccap4h ccap4l reset pca timer/counter x0 00 16bit comparator match enable write to ccap4h reset write to ccap4l 01 1 cmod (d9h) cidl wdte cps1 cps0 ecf x su00042 figure 14. pca watchdog timer pre2 pre1 pre0 lvre ofre dpd wdrun wdmod wdcon (c4h) reset 8bit down counter prescaler osc/2 mov wfeed1,#0a5h mov wfeed2,#5ah watchdog feed sequence shadow register for wdcon wdl (c1h) su00657c wdtof (pcon.2) figure 15. watchdog timer in 87C576 and 80c576 / 83c576 (ea = 0)
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 20 pre2 pre1 pre0 lvre ofre dpd wdrun wdmod wdcon (c4h) 8bit down counter prescaler osc/2 mov wfeed1,#0a5h mov wfeed2,#5ah watchdog feed sequence romcode content wdl wdcon address 2031h 2030h 1 su00658c reset wdtof (pcon.2) 1 figure 16. watchdog timer of 83c576 in watchdog mode (ea = 1, wdmod = 1) pre2 pre1 pre0 lvre ofre dpd wdrun wdmod wdcon (c4h) 8bit down counter prescaler osc/2 mov wfeed1,#0a5h mov wfeed2,#5ah watchdog feed sequence romcode content wdcon address 2030h 0 su00659c wdtof (pcon.2) wdl (c1h) figure 17. watchdog timer of 83c576 in timer mode (ea = 1, wdmod = 0)
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 21 2 2 2 2 2 2 2 pre2 pre1 pre0 000 001 010 011 100 101 110 111 osc/2 64 64 128 256 512 1024 2048 4096 8192 to watchdog down counter decode su00660 figure 18. watchdog prescaler scon address = 98h reset value = 0000 0000b sm0/fe sm1 sm2 ren tb8 rb8 tl rl bit addressable (smod0/1)* symbol function fe framing error bit. this bit is set by the receiver when an invalid stop bit is detected. the fe bit is not cleared by valid frames but should be cleared by software. the smod0 bit must be set to enable access to the fe bit. sm0 serial port mode bit 0, (smod0 must = 0 to access bit sm0) sm1 serial port mode bit 1 sm0 sm1 mode description baud rate** 0 0 0 shift register f osc /12 0 1 1 8-bit uart variable 1 0 2 9-bit uart f osc /64 or f osc /32 1 1 3 9-bit uart variable sm2 enables the automatic address recognition feature in modes 2 or 3. if sm2 = 1 then rl will not be set unless the received 9th data bit (rb8) is 1, indicating an address, and the received byte is a given or broadcast address. in mode 1, if sm2 = 1 then rl will not be activated unless a valid stop bit was received, and the received byte is a given or broadcast address. in mode 0, sm2 should be 0. ren enables serial reception. set by software to enable reception. clear by software to disable reception. tb8 the 9th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. rb8 in modes 2 and 3, the 9th data bit that was received. in mode 1, if sm2 = 0, rb8 is the stop bit that was received. in mode 0, rb8 is not used. tl transmit interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. must be cleared by software. rl receive interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see sm2). must be cleared by software. note: *smod0/1 is located at pcon.6, pcon.7 **f osc = oscillator frequency su00766 bit: 76543210 figure 19. scon: serial port control register
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 22 smod1 smod0 pof lvf gf0 gf1 idl pcon (87h) sm0 / fe sm1 sm2 ren tb8 rb8 ti ri scon (98h) d0 d1 d2 d3 d4 d5 d6 d7 d8 stop bit data byte only in mode 2, 3 start bit set fe bit if stop bit is 0 (framing error) sm0 to uart mode control 0 : scon.7 = sm0 1 : scon.7 = fe su00044 figure 20. uart framing error detection using the automatic address recognition feature allows a master to selectively communicate with one or more slaves by invoking the given slave address or addresses. all of the slaves may be contacted by using the broadcast address. two special function registers are used to define the slave's address, saddr, and the address mask, saden. saden is used to define which bits in the saddr are to be used and which bits are adon't careo. the saden mask can be logically anded with the saddr to create the agiveno address which the master will use for addressing each of the slaves. use of the given address allows multiple slaves to be recognized while excluding others. the following examples will help to show the versatility of this scheme: slave 0 saddr = 1100 0000 saden = 1111 1101 given = 1100 00x0 slave 1 saddr = 1100 0000 saden = 1111 1110 given = 1100 000x in the above example saddr is the same and the saden data is used to differentiate between the two slaves. slave 0 requires a 0 in bit 0 and it ignores bit 1. slave 1 requires a 0 in bit 1 and bit 0 is ignored. a unique address for slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. a unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). thus, both could be addressed with 1100 0000. in a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: slave 0 saddr = 1100 0000 saden = 1111 1001 given = 1100 0xx0 slave 1 saddr = 1110 0000 saden = 1111 1010 given = 1110 0x0x slave 2 saddr = 1110 0000 saden = 1111 1100 given = 1110 00xx in the above example the differentiation among the 3 slaves is in the lower 3 address bits. slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. to select slaves 0 and 1 and exclude slave 2 use address 1110 0100, since it is necessary t make bit 2 = 1 to exclude slave 2. the broadcast address for each slave is created by taking the logical or of saddr and saden. zeros in this result are treated as don't-cares. in most cases, interpreting the don't-cares as ones, the broadcast address will be ff hexadecimal. upon reset saddr (sfr address 0a9h) and saden (sfr address 0b9h) are loaded with 0s. this produces a given address of all adon't careso as well as a broadcast address of all adon't careso. this effectively disables the automatic addressing mode and allows the microcontroller to use standard 80c51 type uart drivers which do not make use of this feature. analog comparators four analog comparators are provided on chip. three comparators have a common negative reference cmpr- and independent positive inputs cmp1+, cmp2+, cmp3+ on port 3. the fourth comparator has independent positive and negative inputs cmp0+ and cmp0- on port 2. the cmp register contains an output and enable bit for each comparator. figure 22 shows the connection of the comparators. when the comparator is enabled, the port should be configured by the user as high impedance.
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 23 sm0 sm1 sm2 ren tb8 rb8 ti ri scon (98h) d0 d1 d2 d3 d4 d5 d6 d7 d8 1 1 1 0 comparator 11 x received address d0 to d7 programmed address in uart mode 2 or mode 3 and sm2 = 1: interrupt if ren=1, rb8=1 and areceived addresso = aprogrammed addresso when own address received, clear sm2 to receive data bytes when all data bytes have been received: set sm2 to wait for next address. su00045 figure 21. uart multiprocessor communication, automatic address recognition cmp register bit definitions cmp.7 enable comparator 3 cmp.6 enable comparator 2 cmp.5 enable comparator 1, cmp.4 enable comparator 0 cmp.3 comparator 3 output (read only) cmp.2 comparator 2 output (read only) cmp.1 comparator 1 output (read only) cmp.0 comparator 0 output (read only) all comparators are disabled automatically in power down mode. in idle mode unused comparators should be disabled by software to save power. a comparator can generate an interrupt that will terminate idle mode when used to drive a pca capture input. the cmpe register contains bits to enable each comparator to drive external output pins or internal pca capture inputs. when the comparator is configured for external output, the user must also configure the output port in one of its output modes. the comparator output is wire-ored with the corresponding port sfr bit, so the sfr bit must also be set by software to enable the output. cmpe register bit definitions cmpe.7 enables comparator 3 to drive cex3 cmpe.6 enables comparator 2 to drive cex2 cmpe.5 enables comparator 1 to drive cex1 cmpe.4 enables comparator 0 to drive cex0 cmpe.3 enables comparator 3 output on p2.3 cmpe.2 enables comparator 2 output on p2.2 cmpe.1 enables comparator 1 output on p2.1 cmpe.0 enables comparator 0 output on p2.0 when 1s are written to cmpe bits 7-4, the comparator outputs will drive the corresponding capture input. when 1s are written to cmpe bits 3-0 the comparator output will also drive the corresponding port 2 pin. if the comparator's enabled to drive the capture input but not the port pin, then the port pin can be used for general purpose i/o. when a comparator output is enabled, the user will need to configure the port for one of its output modes. there are two special function registers associated with the comparators. they are cmp which contains the comparator enables and a bit that can be read by software to determine the state of each comparator's output, and cmpe which controls whether the output from each comparator drives the associated output pin or a capture input associated with one of the pca modules. the cmp registers bits 03 can be read by software to determine the state of the output of each comparator. to do this the associated comparator must be enabled but the output in port 2 can be disabled. this allows easy polling of the comparator output value without the need to use up a port pin. the cmpe register allows the comparator to drive the associated pca module capture input, so that on compare a capture can be generated in the pca. bits 03 of this register enable the comparator output to drive the associated port 2 output circuitry. used as a comparator output, the output mode for this port must be configured for output by the user and the port output sfr bit latch must be set. if the comparator is not enabled to drive the port 2 circuitry, the associated port 2 pin can be used for other i/o. this includes when a comparator is enabled to drive the capture input to a pca module. reduced emi mode there are two bits in the auxr register that can be set to reduce the internal clock drive and disable the ale output. ao (auxr.0) when set turns off the ale output. lo (auxr.1) when set reduces the drive of the internal clock circuitry. both bits are cleared on reset. with lo set the 8xc576 will still operate at 12mhz, and will have reduced emi in the range above 100mhz. 8xc576 reduced emi mode auxr (0x8e) rst txi lo ao ao: turns off ale output. lo: reduces drive of internal clock circuitry. 8xc576 spec'd to 12mhz when lo set. txi: inverts txd when set. rst: software reset.
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 24 + + + + * : will disable pullups on relevant pins p3.4 / cmp1+ p3.3 / cmp2+ p3.2 / cmp3+ p3.5 / cmpr p3.6 / cmp0+ p3.7 / cmp0 ec3dp * ec2dp * ec1dp * ec0dp * c3ro c2ro c1ro c0ro cmp (c0h) ec3tdc ec2tdc ec1tdc ec0tdc ec3od * ec2od * ec1od * ec0od * cmpe (92h) p2.0 / cmp0 p2.1 / cmp1 p2.2 / cmp2 p2.3 / cmp3 enable enable enable enable to cex0 input of pca module 0 to cex1 input of pca module 1 to cex2 input of pca module 2 to cex3 input of pca module 3 su00517c figure 22. analog comparators internal reset internal resets (see figure 1) generated by the power on, low voltage, software (srst), watchdog and oscillator fail detect circuits are self timed to guarantee proper initialization of the 8xc576. reset will be held approximately 24 oscillator periods after normal conditions are detected by all enabled detect circuits. internal resets do not drive rst but will cause missing pulses on ale. analog to digital converter the 8xc576 has a 6 channel10 bit successive approximation a/d converter with separate result registers for each channel. operating modes are provided for single or multiple channel conversions and multiple conversions of a single channel without software intervention. the adc can also be operated in 8 bit mode with faster conversion times. registers adc0hadc5h contain the msbs and adc0ladc5l bits 6 and 7 contain the 2 lsbs of the conversion result for each channel. the adcs register determines which channels are converted in multiple channel modes. if the adcs bit corresponding to a channel is set, that channel is converted, else if the bit is clear the channel is skipped. a/d channel select (adcs) register (reset value = 00h) adcs5 adcs.5 a/d channel 5 select bit adcs4 adcs.4 a/d channel 4 select bit adcs3 adcs.3 a/d channel 3 select bit adcs2 adcs.2 a/d channel 2 select bit adcs1 adcs.1 a/d channel 1 select bit adcs0 adcs.0 a/d channel 0 select bit a/d control (adcon) register (reset value = 00h) adf adcon.7 a/d conversion complete flag adce adcon.6 a/d conversion enable ad8m adcon.5 a/d 8-bit mode amod1 adcon.4 a/d mode select bit 1 amod0 adcon.3 a/d mode select bit 0 asca2 adcon.2 a/d channel address bit 2 asca1 adcon.1 a/d channel address bit 1 asca0 adcon.0 a/d channel address bit 0 amod1 amod0 0 0 single conversion mode channel selected by bits asca2..0 in adcon is converted, the result placed in the associated result registers; adf is set on completion. 0 1 mulitple channel scan mode all channels selected in the adcs register are converted starting with the channel addressed by bits asca2..0 in adon, conversion results are placed in the corres ponding result registers for each channel. adf is set when the last conversion is completed. 1 0 single channel multiple conversion channel selected by bits asca2..0 in adcon is converted 6 times and all 6 results are saved in adc0hadc5h and adc0ladc5l, adf is set when all conversions are complete. 1 1 multiple channel continuous same as multiple channel scan mode but repeats as long as adce=1, adf is set when all channels have been converted once. hardware will prevent the adc from wiriting to the result registers while they are being read. flag adf is set upon completion of a conversion, if the adc interrupt enable bit ead is set, the program will vector to the adc interrupt location when adf is set.
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 25 pwms the pulse width modulator system of the 8xc576 contains two pwm output channels. these channels generate pulses of programmable length and interval. the prescaler and counter are common to both pwm channels. the prescaler is loaded with the complement of the pwmp register during counter overflow, internal reset, and when en/clr# = 0. the repetition frequency is defined by the 8-bit prescaler which clocks the counter. the prescaler division factor = pwmp+1. reading the pwmp gives the current reload value. the actual count of the prescaler cannot be read. the 8-bit counter counts from 0254 inclusive. the value of the counter is compared to the contents of the compare registers pwm0 and pwm1. when the counter compares to the compare register, that register's output goes low. when the counter reaches zero the output is set high unless pwmn = 00h. the duty cycle of each channel is defined by the contents of its compare register and is in the range of 0 to 1, programmed in increments of 1/255. the outputs can be set continuously low by loading pwmn with 00h and continuously high by loading with ffh. the pwm counter is enabled with bit en/clr# of the pwcon register. output to the port pin is separately enabled by setting the pwen bits in the pwcon register. the counter remains active if en/clr# is set even if both pwen bits are reset. the pwm function is reset by a chip reset. in idle mode, the pwm will function as configured by pwcon. in power-down the state of the pwm will freeze when the internal clock stops. if the chip is awakened with an external interrupt, the pwm will continue to function from its state when power-down was entered. the en/clr# bit of pwcon will clear the counter and load the contents of the pwmp into the prescaler when set low. if pwen is set at this time the output will go high unless pwmn is 00h. the repetition frequency is given by: f pwm f osc (510 (1 pwmp)) an oscillator frequency of 12mhz results in a repetition range of 92hz to 23.5khz. the high/low ratio of pwmn is pwmn/(255pwmn) for pwmn values except 255. a pwmn value of 255 results in a high pwmn output. in order for the pwmn output to be used as a standard i/o pin, pwmn must be reset. the pwm counter can still be used as an internal timer by setting en/clr#. pulse width modulator control register bit definitions (pwcon = bch) pwmf pwcon.3 counter overflow flag, must be cleared by software en/clr pwcon.2 counter enable and counter/prescaler reset when low pwe1 pwcon.1 pwm1 output to p2.7 pin enable pwe0 pwcon.0 pwm0 output to p2.6 pin enable auxiliary register bit definitions (auxr =8eh) rst auxr.3 software reset bit txi auxr.2 sio txd invert lo auxr.1 low speed, reduces internal clock drive ao auxr.0 ale off, when set turns off ale interrupt enable 0 (ie0) register ea ie0.7 enable all interrupts ec ie0.6 enable pca interrupt et2 ie0.5 enable timer 2 interrupt es ie0.4 enable serial i/o interrupt et1 ie0.3 enable timer 1 interrupt ex1 ie0.2 enable external interrupt 1 et0 ie0.1 enable timer 0 interrupt ex0 ie0.0 enable external interrupt 0 interrupt enable 1 (ie1) register eob ie1.7 enable obe interrupt eib ie1.6 enable ibf interrupt ead ie1.5 enable adc interrupt ec4 ie1.4 enable pca module 4 interrupt ec3 ie1.3 enable pca module 3 interrupt ec2 ie1.2 enable pca module 2 interrupt ec1 ie1.1 enable pca module 1 interrupt ec0 ie1.0 enable pca module 0 interrupt interrupt priority 0 (ip0) register ip0.7 (reserved) ppc ip0.6 pca interrupt priority pt2 ip0.5 timer 2 interrupt priority ps ip0.4 serial i/o interrupt priority pt1 ip0.3 timer 1 interrupt priority px1 ip0.2 external interrupt 1 priority pt0 ip0.1 timer 0 interrupt priority px0 ip0.0 external interrupt 0 priority interrupt priority 1 (ip1) register pob ip1.7 obe interrupt priority pib ip1.6 ibf interrupt priority pad ip1.5 adc interrupt priority pc4 ip1.4 pca module 4 interrupt priority pc3 ip1.3 pca module 3 interrupt priority pc2 ip1.2 pca module 2 interrupt priority pc1 ip1.1 pca module 1 interrupt priority pc0 ip1.0 pca module 0 interrupt priority
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 26 1/2 pwmp reg 8-bit prescaler 8-bit up counter 8-bit detect output buffer pwm0 pwm1 8-bit detect output buffer f osc internal bus p2.6 p2.7 su00256a figure 23. block diagram of pwms pca interrupt system the pca on most 80c51 family devices provides a single interrupt source, ec (ie.6). the 8xc576 expands the flexibility of the pca by providing additional interrupt sources for each of the five pca modules, ec0 (ie1.0) through ec4 (ie1.4), in addition to the original interrupt source ec (ie.6). any of these sources can be enabled at any time. it is possible for both a module source (ec0 through ec4) to be enabled at the same time that the single source, ec, is enabled. in this case, a module event will generate an interrupt for both the module source and the single source, ec. priority source flag vector 1 int0 ie0 03h highest priority 2 adc adf 3bh 3 timer 0 tf0 0bh 4 int1 ie1 13h 5 timer 1 tf1 1bh 6 serial ri,ti 23h 7 pca0 cc0 43h 8 pca1 cc1 4bh 9 pca2 cc2 53h 10 pca3 cc3 5bh 11 pca4 cc4 63h 12 pca ecf 33h 13 timer 2 tf2/exf2 2bh 14 upi ibf 6bh 15 upi obe 73h lowest priority power control (pcon) register smod1 pcon.7 double baud rate bit smod0 pcon.6 scon.7 access control osf pcon.5 oscillator fail flag pof pcon.4 power off flag lvf pcon.3 low voltage flag wdtof pcon.2 watchdog timeout flag pd pcon.1 power down mode bit idl pcon.0 idle mode bit universal peripheral interface upi mode allows the 8xc576 to function as a slave processor connected to a host cpu bus via port 0. the interface consists of port 0 input and output buffer registers and the upi control/status register (ucs). upi mode is enabled by setting the upi enable bit (ue) in the ucs. when operating in upi mode, port 0 pins should be programmed to high-z (p0m1=1 and p0m2=0) by user firmware. access to port 0 is controlled by inputs wr , rd , cs , and a0. rd and wr are the external read and write strobes controlled by the host cpu. cs is the chip select input, normally a decoded address from the host cpu bus, which qualifies rd and wr (these pins have no effect when cs =1). the a0 pin is an address input from the host cpu which selects either the port 0 output buffer or the ucs register to be output during a read operation. during a write operation, the value of the a0 pin is latched in the af flag in the ucs register. the following is a summary of the upi data control inputs: cs rd wr a0 0 0 1 0 read port 0 output buffer, clear obf/set obe 0 0 1 1 read upi control/ status register 0 1 0 0 write data to input buffer set ibf, clear af 0 1 0 1 write command to input buffer set ibf, af 1 x x x disable input/output upi control status register (ucs, reset value = 00h) ucs.7 st7 user defined status bit ucs.6 st6 user defined status bit ucs.5 st5 user defined status bit ucs.4 st4 user defined status bit ucs.3 ue upi enable bit if ue=1, upi is enabled (read only af, ibf, and obe/obf), if ue=0, upi is disabled and port 0 functions normally. ucs.2 af address flag contains status of the a0 (address) pin during the last write. if a0=0, the input buffer should be interpreted as data by the 8xc576 software, if a0=1, the input buffer should be interpreted as a command. usc.1 ibf input buffer full flag set by hardware on trailing (rising) edge of wr when cs =0, cleared by hardware when port 0 sfr is read (by the 8xc576 software). usc.0 obe/obf output buffer full flag set by hardware during writes (by 8xc576 software) to the port 0 sfr, set/cleared by hardware on the trailing (rising) edge of rd when cs =0 and a0=0. note: this bit is defined as obe (1=empty) when read by the mcu, and, as obf (efull) when read by the external host. the ibf and obf flag bits reflect the status of the input/output buffers. the host cpu writes to the 8xc576 by driving data on the external bus connected to port 0 and strobing the wr pin while cs =0. the wr strobe latches port 0 data in the input buffer and sets the ibf flag on the trailing (rising) edge. when the 8xc576 reads from port 0 in upi mode, it reads from the input buffer and
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 27 clears the ibf. when the 8xc576 writes to port 0 in upi mode, it writes to the output buffer which sets the obf and clears the obe flag. the host cpu can read the output buffer or the ucs register enabling the port 0 drivers, the obf flag is cleared and the obe flag is set when the output buffer is read. when the upi is enabled, the af, ibf, and obe/obf flags are read-only, and thus can only be modified by specific hardware events. the upi runs in idle mode. it can interrupt the part out of idle mode for all upi write and data read operations. it will not interrupt out of idle mode for a ucs register read operation. oscillator characteristics xtal1 and xtal2 are the input and output, respectively, of an inverting amplifier. the pins can be configured for use as an on-chip oscillator, as shown in the logic symbol, page 4. to drive the device from an external clock source, xtal1 should be driven while xtal2 is left unconnected. there are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. however, minimum and maximum high and low times specified in the data sheet must be observed. idle mode in idle mode, the cpu puts itself to sleep while all of the on-chip peripherals stay active. the instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. the cpu contents, the on-chip ram, and all of the special function registers remain intact during this mode. the idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. also see upi section. power-down mode in the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed. only the contents of the on-chip ram are preserved. the control bits for the reduced power modes are in the special function register pcon. power-down mode can be terminated with either a hardware reset or external interrupt. with an external interrupt int0 or int1 must be enabled and configured as level sensitive. holding the pin low restarts to oscillator and bringing the pin back high completes the exit. power-down mode can be disabled by the dpd bit in the wdcon register. reset and waking up from power-down will also enable the dpd bit, therefore, the dpd bit must be cleared again before the power-down mode. design considerations at power-on, the voltage on v cc must come up with rst low for a proper start-up. table 2 shows the state of i/o ports during low current operating modes. table 2. external pin status during idle and power-down modes mode program memory ale psen port 0 port 1 port 2 port 3 idle internal 1 1 data data data data idle external 1 1 float data address data power-down internal 0 0 data data data data power-down external 0 0 float data data data
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 28 rom code submission when submitting rom code for the 83c576, the following must be specified: 1. 8k byte user rom data 2. 32 byte rom encryption key 3. rom security bits 4. the watchdog timer parameters. (see watchdog timer specifications for definition of wdl and wdcon bits.) address content bit(s) comment 0000h to 1fffh data 7:0 user rom data 2000h to 201fh key 7:0 rom encryption key ffh = no encryption 2020h sec 0 rom security bit 1 0 = enable security 1 = disable security 1 rom security bit 2 0 = enable security 1 = disable security 2030h wdcon 7:5 pre2:0 4 lvre 3 ofre 2 dpd 1 wdrun = 0, not rom coded 0 wdmod 2031h wdl 7:0 watchdog autoload value (see specification) security bit 1: when programmed, this bit has two effects on masked rom parts: 1. external movc is disabled, and 2. ea is latched on reset. security bit 2: when programmed, this bit inhibits verify user rom. if the rom code file does not include the options, the following information must be included with the rom code. for each of the following, check the appropriate box and send to philips along with the code: security bit #1: enabled disabled security bit #2: enabled disabled encryption: no yes if yes, must send key file. watchdog/timer modes: watchdog mode timer mode prescaler value: (value = 64, 128, 256, 512, 1024, 2048, 4096, 8192) value autoload value (range 0255): low voltage reset (value 0 or 1): oscillator fail reset (value 0 or 1): power-down (value 0 or 1):
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 29 absolute maximum ratings 1, 2, 3 parameter rating unit operating temperature under bias 55 to +125 c storage temperature range 65 to +150 c voltage on ea /v pp pin to v ss 0 to +13.0 v voltage on any other pin to v ss 0.5 to +6.5 v maximum i ol per i/o pin 15 ma power dissipation (based on package heat transfer limitations, not device power consumption) 1.5 w notes: 1. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions other than those described in the ac and dc electrical characteri stics section of this specification is not implied. 2. this product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. parameters are valid over operating temperature range unless otherwise specified. all voltages are with respect to v ss unless otherwise noted.
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 30 dc electrical characteristics t amb = 0 c to +70 c, 40 c to +85 c, and 40 c to +125 c; v cc = 5v 10%, v ss = 0v test limits symbol parameter conditions min typ 1 max unit v il input low voltage (except port 1, ea ) 0.5 0.2v cc 0.1 v v il1 input low voltage (ea ) 0.5 0.2v cc 0.45 v v il2 input low voltage (port 1) 0.5 0.3v cc v v ih input high voltage (except port 1, xtal1, rst) i ih < 2ma 0.2v cc +0.9 v cc +0.5 v v ih1 input high voltage (xtal1, rst, port 1) i ih < 2ma 0.7v cc v cc +0.5 v hys hysteresis voltage (port 1) 200 mv v ol output voltage low (ports 1, 2, 3) i ol = 1.6ma 0.45 v v ol1 output voltage low (ports 0, ale, psen ) i ol = 3.2ma 0.45 v v oh output voltage high (ports 1, 2, 3 in push-pull mode) i oh = 1.6ma v cc 1.0 v v oh1 output voltage high (port 0, ale, psen ) i oh = 3.2ma v cc 0.7 v v oh2 output voltage high in weak pullup mode (port 0, 2, 3) i oh = 10 m a v cc 1.0 v v io offset voltage comparator inputs 35 +35 mv v cr common mode range comparator inputs 0 v cc v i il logical 0 input current (ports 0, 2, 3) (weak pull-up) v in = 0.45v 250 m a i ih input pulldown current (port 0, port2 in open drain mode) 0.45 < v in < v cc 2 40 m a i l2 input leakage current (ea , p0. 2. 3 high-z) 0.45 < v in < v cc 10 +10 m a i la input leakage current comparator/adc inputs 0 < v in < v cc 1.0 +1.0 m a i cc power supply current: 7 active mode @ 16mhz 5 idle mode @ 16mhz power-down mode see note 6 20 8 5 30 12 75 ma ma m a r rst internal reset pull-up resistor v in = 0v 50 200 k w v low low v cc detect voltage 3.75 4.25 v c io pin capacitance 9 f = 1mhz 15 pf notes: 1. typical ratings are not guaranteed. the values listed are at room temperature, 5v. 2. capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the v ol s of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus oper ations. in the worst cases (capacitive loading > 100pf), the noise pulse on the ale pin may exceed 0.8v. in such cases, it may be desirable to qualify ale with a schmitt trigger, or use an address latch with a schmitt trigger strobe input. i ol can exceed these conditions provided that no single output sinks more than 5ma and no more than two outputs exceed the test conditions. 3. capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the 0.9v cc specification when the address bits are stabilizing. 4. pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. the transition curren t reaches its maximum value when v in is between v ih and v il . 5. i cc max at other frequencies can be determined from figure 33. 6. see figures 34 through 37 for i cc test conditions. 7. load capacitance for port 0, ale, and psen = 100pf, load capacitance for all other outputs = 80pf. 8. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10ma maximum i ol per 8-bit port: 26ma maximum total i ol for all outputs: 71ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 9. 20pf max for cerdip package; 15pf max for all other packages.
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 31 a/d converter dc electrical characteristics t amb = 0 c to +70 c, 40 c to +85 c, and 40 c to +125 c; v cc = 5v 10%, v ss = 0v test limits symbol parameter conditions min max unit static characteristics r resolution monotonic with no missing codes 10 bits il e integral non-linearity error 2, 5, 8 2 lsb dl e differential non-linearity error 2, 3, 4, 7, 8 1 lsb fs e full scale error 2, 8 3 lsb os e offset error 2, 6, 8 2 lsb dynamic characteristics t adc conversion time (including sampling time) 48t cy m s t ads sampling tme 8t cy m s analog input characteristics av in analog input voltage av ss 0.2 av dd + 0.2 v c ia analog input capacitance 15 pf m ctc channel-to-channel matching 7 1 lsb c t crosstalk between inputs of port 1 7 0100khz 60 db power requirements av cc /v ref+ analog supply and reference voltage av cc = v cc 0.2 4.0 6.0 v ai cc analog supply current: operating: (16mhz) av cc = 6.0v 1.2 ma notes: 1. the following condition must not be exceeded: v dd 0.2v < av dd < v dd + 0.2v. 2. conditions: av ss = 0v; av cc = 4.997v; v cc = 5.0v. 3. the differential non-linearity (dl e ) is the difference between the actual step width and the ideal step width. (see figure 24). 4. the adc is monotonic; there are no missing codes. 5. the integral non-linearity (il e ) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset error. (see figure 24). 6. the offset error (os e ) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and a straight line which fits the ideal transfer curve. (see figure 24). 7. guaranteed by design. 8. to meet error specification, analog input voltage must be less than 1v/ms. slew rate max (av cc 1023) 1000 4 (12 osc freq (mhz)) (v ms) for 16mhz @ 5.0v slew rate = 1.6v/ms.
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 32 1 0 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 code out (2) (1) (5) (4) (3) 1 lsb (ideal) offset error os e offset error os e gain error g e av in (lsb ideal ) 1 lsb = av ref+ av ref 1024 (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential non-linearity (dl e ). (4) integral non-linearity (il e ). (5) center of a step of the actual transfer curve. su00710 full scale error fs e figure 24. adc conversion characteristic
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 33 ac electrical characteristics t amb = 0 c to +70 c, 40 c to +85 c, and 40 c to +125 c; v cc = 5v 10%, v ss = 0v 1, 2 variable clock symbol figure parameter min max unit 1/t clcl 25 oscillator frequency: speed version 8xc576 e 6 16 mhz oscf oscillator fail detect frequency 0.6 5.5 mhz tr comparator response time 10 m s t lhll 25 ale pulse width 2t clcl 40 ns t avll 25 address valid to ale low t clcl 40 ns t llax 25 address hold after ale low t clcl 30 ns t lliv 25 ale low to valid instruction in 4t clcl 100 ns t llpl 25 ale low to psen low t clcl 30 ns t plph 25 psen pulse width 3t clcl 45 ns t pliv 25 psen low to valid instruction in 3t clcl 105 ns t pxix 25 input instruction hold after psen 0 ns t pxiz 25 input instruction float after psen t clcl 25 ns t aviv 25 address to valid instruction in 5t clcl 105 ns t plaz 25 psen low to address float 10 ns data memory t rlrh 26, 27 rd pulse width 6t clcl 100 ns t wlwh 26, 27 wr pulse width 6t clcl 100 ns t rldv 26, 27 rd low to valid data in 5t clcl 165 ns t rhdx 26, 27 data hold after rd 0 ns t rhdz 26, 27 data float after rd 2t clcl 60 ns t lldv 26, 27 ale low to valid data in 8t clcl 150 ns t avdv 26, 27 address to valid data in 9t clcl 165 ns t llwl 26, 27 ale low to rd or wr low 3t clcl 50 3t clcl +50 ns t avwl 26, 27 address valid to wr low or rd low 4t clcl 130 ns t qvwx 26, 27 data valid to wr transition t clcl 50 ns t whqx 26, 27 data hold after wr t clcl 50 ns t rlaz 26, 27 rd low to address float 0 ns t whlh 26, 27 rd or wr high to ale high t clcl 40 t clcl +40 ns external clock t chcx 29 high time 20 ns t clcx 29 low time 20 ns t clch 29 rise time 20 ns t chcl 29 fall time 20 ns shift register t xlxl 28 serial port clock cycle time 12t clcl ns t qvxh 28 output data setup to clock rising edge 10t clcl 133 ns t xhqx 28 output data hold after clock rising edge 2t clcl 60 ns t xhdx 28 input data hold after clock rising edge 0 ns t xhdv 28 clock rising edge to input data valid 10t clcl 133 ns notes: 1. parameters are valid over operating temperature range unless otherwise specified. 2. load capacitance for port 0, ale, and psen = 100pf, load capacitance for all other outputs = 80pf. 3. interfacing the 83c576/87C576 to devices with float times up to 45ns is permitted. this limited bus contention will not cause damage to port 0 drivers.
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 34 upi ac electrical characteristics t amb = 0 c to +70 c, 40 c to +85 c, and 40 c to +125 c; v cc = 5v 10%, v ss = 0v symbol parameter min max unit t ar cs , a setup to rd 0 ns t ra cs , a hold after rd 35 ns t rr rd pulse width 35 ns t ad cs , a to data out delay 45 ns t rd rd to data out delay 35 ns t df rd to data float delay (guaranteed by design) 30 ns t aw cs , a setup to wr 0 ns t wa cs , a hold after wr 15 ns t ww wr pulse width 45 ns t dw data setup to wr 5 ns t wd data hold after wr 25 ns explanation of the ac symbols each timing symbol has five characters. the first character is always `t' (= time). the other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. the designations are: a address c clock d input data h logic level high i instruction (program memory contents) l logic level low, or ale p psen q output data r rd signal t time v valid w wr signal x no longer a valid logic level z float examples: t avll = time for address valid to ale low. t llpl =time for ale low to psen low. t pxiz ale psen port 0 port 2 a0a15 a8a15 a0a7 a0a7 t avll t pxix t llax instr in t lhll t plph t lliv t plaz t llpl t aviv su00006 t pliv figure 25. external program memory read cycle
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 35 ale psen port 0 port 2 rd a0a7 from ri or dpl data in a0a7 from pcl instr in p2.0p2.7 or a8a15 from dpf a0a15 from pch t whlh t lldv t llwl t rlrh t llax t rlaz t avll t rhdx t rhdz t avwl t avdv t rldv su00025 figure 26. external data memory read cycle t llax ale psen port 0 port 2 wr a0a7 from ri or dpl data out a0a7 from pcl instr in p2.0p2.7 or a8a15 from dpf a0a15 from pch t whlh t llwl t wlwh t avll t avwl t qvwx t whqx su00069 figure 27. external data memory write cycle
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 36 012345678 instruction ale clock output data write to sbuf input data clear ri valid valid valid valid valid valid valid valid set ti set ri t xlxl t qvxh t xhqx t xhdx t xhdv su00027 123 0 4567 figure 28. shift register mode timing v cc 0.5 0.45v 0.7v cc 0.2v cc 0.1 t chcl t clcl t clch t clcx t chcx su00009 figure 29. external clock drive v cc 0.5 0.45v 0.2v cc +0.9 0.2v cc 0.1 note: ac inputs during testing are driven at v cc 0.5 for a logic `1' and 0.45v for a logic `0'. timing measurements are made at v ih min for a logic `1' and v il max for a logic `0'. su00010 figure 30. ac testing input/output v load v load +0.1v v load 0.1v v oh 0.1v v ol +0.1v note: timing reference points for timing purposes, a port is no longer floating when a 100mv change from load voltage occurs, and begins to float when a 100mv change from the loaded v oh /v ol level occurs. i oh /i ol 20ma. su00011 figure 31. float waveform
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 37 t ar ao, cs rd wr su00518 t aw t ra t wa t rr t ww t ad t rd t dw t df t wd d0d7 figure 32. upi read/write cycles frequency (mhz) max active typ active max idle typ idle i cc (ma) 045 10 151620 30 25 20 15 10 5 0 su00245 figure 33. i cc vs. freq valid only within frequency specifications of the device under test v cc ea rst xtal1 xtal2 v ss v cc v cc i cc (nc) clock signal su00661 av cc av ss figure 34. i cc test condition, active mode all other pins are disconnected
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 38 v cc ea rst xtal1 xtal2 v ss v cc v cc i cc (nc) clock signal su00662 av ss av cc av cc figure 35. i cc test condition, idle mode all other pins are disconnected v cc 0.5 0.45v 0.7v cc 0.2v cc 0.1 t chcl t clcl t clch t clcx t chcx su00009 figure 36. clock signal waveform for i cc tests in active and idle modes t clch = t chcl = 5ns v cc ea rst xtal1 xtal2 v ss v cc v cc i cc (nc) su00663a av ss av cc figure 37. i cc test condition, power down mode all other pins are disconnected. v cc = 2v to 5.5v
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 39 eprom characteristics to put the 87C576 in the parallel eprom programming mode, psen must be held high during power up, then driven low with reset active. the 87C576 is programmed by using a modified quick-pulse programming ? algorithm. the 87C576 contains two signature bytes that can be read and used by an eprom programming system to identify the device. the signature bytes identify the device as an 87C576 manufactured by philips. table 3 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. the circuit configuration and waveforms for quick-pulse programming are shown in figures 38 and 39. figure 40 shows the circuit configuration for normal program memory verification. on-board programming (obp) the on-board programming facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the 87C576 through the serial port. the obp function is invoked by having the ea /v pp pin at the v pp voltage level at the time that the part exits reset. the obp function only requires that the txd, rxd, v ss , v cc , and v pp pins be connected to an external circuit in order to use this feature. the obp feature provides for the use of a wide range of baud rates independent of the oscillator frequency used. it is also adaptable to a wide range of oscillator frequencies. the obp facility provides for both auto-echo and no-echo of received characters. the obp feature requires that an initial character, an uppercase u, be sent to the 87C576 to establish the baud rate to be used. once baud rate initialization has been performed, the obp facility only accepts intel hex records. the record-type field of these hex records are used to indicate either commands or data for the obp facility. the maximum number of data bytes in a record is limited to 16 (decimal). these commands/data are summarized below: record type command/data function 00 data record, programs the part with data indicated in record starting with load address in the record 01 eof record, no operation 02 specify timing parameters rec length = 3 bytes load address = 0000 1st byte = timer count for 50 m s programming pulse 2nd byte = timer count for 10 m s delay between pulses 3rd byte = 0ah 03 program security bits rec length = 1 byte load address = 0000 1st byte = sec bit values (xxxx xxb2b1) 04 display contents of user eprom array rec length = 00 load address = 0000 05 verify security bit status rec length = 00 load address = 0000 quick-pulse programming (parallel) the setup for microcontroller quick-pulse programming is shown in figure 38. note that the 87C576 is running with a 4 to 6mhz oscillator. the reason the oscillator needs to be running is that the device is executing internal address and program data transfers. the address of the eprom location to be programmed is applied to ports 3 and 2, as shown in figure 38. the code byte to be programmed into that location is applied to port 0. rst, psen and pins of ports 2 and 1 specified in table 3 are held at the `program code data' levels indicated in table 3. the ale/prog is pulsed low 25 times as shown in figure 39. to program the encryption table, repeat the 25 pulse programming sequence for addresses 0 through 1fh, using the `pgm encryption table' levels. do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. to program the security bits, repeat the 25 pulse programming sequence using the `pgm security bit' levels. after one security bit is programmed, further programming of the code memory and encryption table is disabled. however, the other security bit can still be programmed. note that the ea /v pp pin must not be allowed to go above the maximum specified v pp level for any amount of time. even a narrow glitch above that voltage can cause permanent damage to the device. the v pp source should be well regulated and free of glitches and overshoot. program verification if security bit 2 has not been programmed, the on-chip program memory can be read out for program verification. the address of the program memory locations to be read is applied to ports 3 and 2 as shown in figure 40. the other pins are held at the `verify code data' levels indicated in table 3. the contents of the address location will be emitted on port 0. external pull-ups are required on port 0 for this operation. if the encryption table has been programmed, the data presented at port 0 will be the exclusive nor of the program byte with one of the encryption bytes. the user will have to know the encryption table contents in order to correctly decode the verification data. the encryption table itself cannot be read out. reading the signature bytes the signature bytes are read by the same procedure as a normal verification of locations 030h and 031h, except that p1.0 and p1.1 need to be pulled to a logic low. the values are: (030h) = 15h indicates manufactured by philips (b6h) = b6h indicates 87C576 program/verify algorithms any algorithm in agreement with the conditions listed in table 3, and which satisfies the timing specifications, is suitable. ? trademark phrase of intel corporation.
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 40 table 3. eprom programming modes mode rst psen ale/prog ea /v pp p2.7 p2.6 p1.1 p1.0 read signature 0 0 1 1 0 0 0 0 program code data 0 0 0* v pp 1 0 1 1 verify code data 0 0 1 1 0 0 1 1 pgm encryption table 0 0 0* v pp 1 0 1 0 pgm security bit 1 0 0 0* v pp 1 1 1 1 pgm security bit 2 0 0 0* v pp 1 1 0 0 notes: 1. `0' = valid low for that pin, `1' = valid high for that pin. 2. v pp = 12.75v 0.25v. 3. v cc = 5v 10% during programming and verification. * ale/prog receives 5 programming pulses while v pp is held at 12.75v. each programming pulse is low for 50 m s ( 10 m s) and high for a minimum of 10 m s.
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 41 a0a7 0 1 1 46mhz +5v pgm data +12.75v 5 50 m s pulses to ground 0 1 0 a8a12 p3 rst p1.0 p1.1 xtal2 xtal1 v ss v cc p0 ea /v pp ale/prog psen p2.7 p2.6 p2.0p2.4 87C576 su00257b +5v av cc av ss figure 38. programming configuration ale/prog: ale/prog: 1 0 1 0 5 pulses 50 m s+ 10 10 m s min su00664 figure 39. prog waveform a0a7 0 1 1 46mhz +5v pgm data 1 1 0 0 enable 0 a8a12 p3 rst p1.0 p1.1 xtal2 xtal1 v ss v cc p0 ea /v pp ale/prog psen p2.7 p2.6 p2.0p2.4 87C576 su00258b +5v av cc av ss figure 40. program verification
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 42 eprom programming and verification characteristics t amb = 21 c to +27 c, v cc = 5v 10%, v ss = 0v (see figure 41) symbol parameter min max unit v pp programming supply voltage 12.5 13.0 v i pp programming supply current 50 ma 1/t clcl oscillator frequency 4 12 mhz t avgl address setup to prog low 48t clcl t ghax address hold after prog 48t clcl t dvgl data setup to prog low 48t clcl t ghdx data hold after prog 48t clcl t ehsh p2.7 (enable ) high to v pp 48t clcl t shgl v pp setup to prog low 10 m s t ghsl v pp hold after prog 10 m s t glgh prog width 40 60 m s t avqv address to data valid 48t clcl t elqz enable low to data valid 48t clcl t ehqz data float after enable 0 48t clcl t ghgl prog high to prog low 10 m s programming * verification * address address data in data out logic 1 logic 1 logic 0 t avqv t ehqz t elqv t ehsh t shgl t ghsl t glgh t ghgl t avgl t ghax t dvgl t ghdx p3.0p3.7 p2.0p2.4 port 0 ale/prog ea /v pp p2.7 enable su00207 * for programming verification see figure 38. for verification conditions see figure 40. figure 41. eprom programming and verification
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 43 dip40: plastic dual in-line package; 40 leads (600 mil) sot129-1
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 44 plcc44: plastic leaded chip carrier; 44 leads sot187-2
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 45 qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2
philips semiconductors product specification 83c576/87C576 80c51 8-bit microcontroller family 8k/256 otp/rom, 6 channel 10-bit a/d, 4 comparators, failure detect circuitry, watchdog timer 1998 jun 04 46 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 1998 all rights reserved. printed in u.s.a. date of release: 06-98 document order number: 9397 750 04024
data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

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